1. An active current mirror means that ___________.
Answers:
• active devices are used as load
• active devices are used as elements
• it is always active in the circuit
• None of these
2. Floating point data types provide an approximation of ___________.
Answers:
• complex numbers
• rational numbers
• even numbers
• real numbers
3. For an npn Bipolar Transistor, gm ___________.
Answers:
• is dependent on input voltage
• is dependent on IC
• is independent of the process
• All of these
4. Contacts between the metal layers are known as _____________.
Answers:
• contacts
• cuts
• vias
• None of the above
5. How many Pass transistors can be connected in a series?
Answers:
• 3
• 4
• 5
• 6
6. A signal data object in VHDL is an object with_______________.
Answers:
• a past history of values
• a present history of values
• a future history of values
• a history without any values
7. For a given total bias current, the gain of a differential pair is________ more than the CS Stage.
Answers:
• 1/2
• 1/4
• 1/3
• 1/√2
8. A fast CMOS circuit requires that the gm___________. (Where gm means transconductance).
Answers:
• should be small
• should be high
• should be independent of gm
• should vary inversely with speed
9. High Electron Mobility Transistors(HEMT) are formed using alternating layers of _______________.
Answers:
• GaAs and silicon
• GaAs and boron
• GaAs and AlGaAs
• GaAs and germanium GaAs
10. For the Orbit Process, the n-active and p-active regions have_________.
Answers:
• small capacitance
• large capacitance
• infinite capacitance
• negligible capacitance
59 NOT Answered Yet Test Questions:
(hold on, will be updated soon)11. What is Metallization in IC Fabrication?
Answers:
• It is a process in which a layer of metal is deposited on a silicon wafer
• It is a process in which a wafer is sliced by a metal
• It is a process by which the components of an IC are inter connected by an aluminum conductor
• It is a process in which a metal base is formed below the surface of a wafer
12. The separation between the Thinox Regions is of __________ .
Answers:
• 2λ
• 3λ
• 4λ
• 5λ
13. If length (L) and width (W) are both scaled down by α, the area is scaled ___________. (Power Speed Product PT)
Answers:
• down by α
• down by α2
• up by α
• None of these
14. What exactly is Behavioral Modeling in VHDL?
Answers:
• A set of concurrent statements
• A set of interconnected components
• A set of sequential program statements
• A set of cumulative statements
15. Latch up introduces_________.
Answers:
• a low resistance path between adjacent devices
• a low resistance path between the source and the drain
• a low resistance path between the power supply and the ground
• None of the above
16. What is Generic Array Logic(GAL) based on?
Answers:
• PROMs
• EAROMs
• EEPROMs
• Flash Memory
17. The Double Metal MOS process is used to ____________.
Answers:
• increase the metal area
• increase the VDD area
• increase the VSS area
• None of the above
18. In general, VDD and VSS are always distributed upon ____________.
Answers:
• Polysilicon layers
• Metal Layers
• Either of the above
• None of these
19. MOS current sources are used to generate __________.
Answers:
• current Mirrors
• current Steering Circuits
• current Sink
• All of these
20. Which execution platform is used for a behaviour-level VHDL?
Answers:
• Simulator
• Operating system
• Debugger
• Real time operating system
21. The Cascode structure ___________.
Answers:
• has low output impedance
• has high output impedance
• is the product of output impedance of the two stages used
• None of the above
22. Which one of the following statements is not correct about an entity in VHDL?
Answers:
• An entity is a description of the interface between a design and an external environment
• An entity defines the input and output ports of a design
• One entity has only one architecture
• A design can contain more than one entity
23. Which one of the following is not a mode for ports in VHDL?
Answers:
• IN
• OUT
• Buffer
• Tri-state
24. If length (L) and width (W) are both scaled down by α, the area is scaled down by __________.
Answers:
• α
• α2
• α/2
• None of the above
25. In the Folded Cascode structure, ____________.
Answers:
• the current is folded up
• the current is folded down
• both of the above
• none of the above
26. What does the Programmable Logic Array(PLA) consist of?
Answers:
• A programmable AND array and a programmable OR array
• A programmable AND array and a fixed OR array
• A fixed AND array and a programmable OR array
• Fixed AND and OR arrays
27. What function does the scalar data type perform in VHDL?
Answers:
• It provides element values
• It does not provide element values
• It provides access to objects of a given type
• It provides access to objects that contain a sequence of values
28. What is the function of the Alias statement?
Answers:
• It declares an alternate name for an existing named entity
• It declares the same name again for an existing named entity
• It declares a different name for a different entity
• It declares the already used name for a different entity
29. Which of the following is the fastest technology in terms of propagation delay?
Answers:
• CMOS
• ECL
• BiCMOS
• GaAs
30. When is the Boundary Scan Test (BST) used?
Answers:
• It is used to test the MOS function
• It is used to test the fan-out of TTL family
• It is used to test the output impedance of MOS
• It is used to resolve problems associated with the testing of boards carrying VLSI circuits
31. Which one of the following is not a sequential statement in VHDL?
Answers:
• The Next statement
• The Exit statement
• The If statement
• The Block statement
32. LSI and VLSI devices use_____________ technology.
Answers:
• TTL
• ECL
• MOS
• CMOS
33. Which one of the following is a concurrent statement?
Answers:
• The main statement
• The end statement
• The process statement
• The signal statement
34. Photolithography in IC Fabrication is___________.
Answers:
• the deposition of oxide in selective areas
• the selective removal of oxide in the desired areas
• a process for ion implantation
• a process for annealing
35. In the BiCMOS process, the basic inverter is made by __________.
Answers:
• using mos as switch and BJT as driver
• using mos as driver and BJT as switch
• using either of the two as driver or switch
• None of these
36. QHDL(Hardware Description Language) is used for _____________.
Answers:
• software design of circuits
• hardware design of circuits
• operating system design of circuits
• real time operating system design of circuits
37. Under what condition does the Frenkel defect take place?
Answers:
• A vacancy in the lattice created due to a missing atom
• A silicon atom in an interstitial lattice site with an associated vacancy
• A non silicon atom in an interstitial lattice site with an associated vacancy
• A vacancy in the lattice created due to a missing molecule
38. Which among the following conditions qualifies for a Latch-up in CMOS circuit condition?
Answers:
• When a high resistance path is established between the drain and the source
• When a high resistance path is established between the drain and the gate
• When a low resistance path is established between the drain and the source
• When a low resistance path is established between the drain and the gate
39. If length (L) and width (W) are both scaled down by α, the area is scaled ___________. ron
Answers:
• down by α resistance
• down by α2
• up by α
• None of these
40. Stick diagrams are used to __________.
Answers:
• convey the presence of Metal
• convey the presence of Gate
• convey the presence of Contact
• convey the layer information
41. Which kind of problem is eliminated by the NMOS superbuffers?
Answers:
• Symmetry of the conventional inverter
• Low output problem of the conventional inverter
• Asymmetry of the conventional inverter
• High output problem of the conventional inverter
42. In the Cascode structure, the maximum voltage gain is roughly equal to ____________.
Answers:
• the sum of the intrinsic gain of the transistors
• the product of the intrinsic gain of the transistors
• the square of the intrinsic gain of the transistors
• None of these
43. In VHDL, the prefix "V" stands for ___________________.
Answers:
• VHSIC (very high switching integrated circuit)
• VHSIC (very high speed integrated circuit)
• VHSIC (very high speed integrated configuration)
• VHSIC (verilog high switching integrated circuit)
44. What is the body effect on the input impedance of the Common Gate Configuration?
Answers:
• It decreases the input impedance
• It increases the input impedance
• The input impedance is independent of the body effect
• None of these
45. Which of the following can act as a dopant for the formation of N-type gallium arsenide material?
Answers:
• Boron
• Silicon
• Germanium
• Phosphorous
46. Which of the following parameters is advantageous in the case of BiCMOS technology?
Answers:
• Power dissipation
• High o/p drive current
• High noise margin
• Low output drive current
47. The two metal layers are laid in a way that ______________.
Answers:
• the conductors are always parallel
• the conductors are always orthogonal
• the conductors are always touching
• None of the above
48. In which condition is the Case statement used?
Answers:
• When the output of design depends on the value of one signal expression
• When the behavior of design depends on the value of one signal expression
• When the output of design depends on the value of two signal expression
• When the behavior of design depends on the value of two signal expressions
49. Which kind of signal is converted into in the common source arrangement of the transistor?
Answers:
• Voltage signal
• Current signal
• Power signal
• No idea
50. MOS in the Common Gate Configuration provides___________.
Answers:
• Inverted gain
• Non inverted gain
• Gain less than one
• Unity gain
